Interview Question 47: Multi Clock Sync Pulse

 Design a module as shown below. The input sync_A gets asserted for some (say 3) clocks in the clk_A domain. The output sync_B should also assert for exactly the same number of clocks but in the clk_B domain.

The timing diagram is shown below.

Followup questions:

- Is fA/fB ratio fixed or it is unknown?

  .The answer to this question will decide which CDC approach you should take.

- Is the number of clocks fixed or variable or it can vary on the fly or is it configurable?

  . The answer to this question will decide which approach you take?

Interview Question 46: What is wrong with this design?

 Study the provided block diagram of a chip-level design. Each square has one clock delay associated with it. What can go wrong with this type of design? How will you fix it? How it will affect the overall design?

Interview Question 45: Find faster clock

 Design a module that finds the faster clock between two different clocks. The output A_faster_than_B asserts "1" when fA > fB and asserts "0" when fB > fA along with valid. 

Followup questions:

- How will you handle when clocks are almost the same or the same? How will you indicate the output in this case?

- How will update the design if asked to find and indicate the frequency of the clocks?