This is a simple microarchitecture problem. You are asked to design a data splitter. It accepts 700-bit-wide data and outputs 1 or more chunks. In the worst case, it should spit out 4 data chunks.

The diagram below shows slightly more details. You need to create a struct to make sure you understand the problem correctly. The incoming data contains 32 chunks of 20-bit data (pointers??). One field in the header indicates the number of data chunks. It decides whether to output just one chunk of data or multiple chunks. The diagram shows the worst-case scenario when num_data=32. Each chunk can carry 8 pieces of data, so you will end up transmitting 4 chunks of data over 4 clocks.

Some fields in the header also indicate the destination. They will be used to decide where to send the data: Data_Out_0 or Data_Out_1.

With this information, create a microarchitecture.

Issue 1: As you are creating 4 clocks' worth of output transactions with 1 clock of input data, you will have a backpressure issue. How will you solve it? Where will you put your FIFOs?

Issue 2: When this splitter is transmitting data on one output port, the other output port is unused for 4 or more clocks. How do you modify the design so that both output ports stay busy?

Imagine a worst-case scenario in which inputs arrive in such a way that their output ports alternate. You can see that if one output port back pressures, the second port stalls or starves, even if it is not congested. How to avoid this head-of-the-line blocking? 

Interview Question 45: Find faster clock

 Design a module that finds the faster clock between two different clocks. The output A_faster_than_B asserts "1" when fA > fB and asserts "0" when fB > fA along with valid. 

Followup questions:

- How will you handle when clocks are almost the same or the same? How will you indicate the output in this case?

- How will update the design if asked to find and indicate the frequency of the clocks?

Interview Question 44: Fix the Timing Issue

Consider a design where two modules on the chip communicate with each other over a bus using a protocol like AXI. Data from block 1 is consumed by block 2 when both valid and ready are asserted.

The timing shown below shows how this protocol works.

After Synthesis and Place & Route, you find out that a valid/ready handshake is not meeting timing. How will you fix it?

These two blocks are IPs from a vendor. Though you have access to RTL, you can not change them radically. You are allowed to add some glue logic in between. This is a fairly open-ended question. Your past experience will result in multiple ideas.

How will you attach this problem in these two scenarios?

a) Timing violation is just 5-10% of the clock period.

b) Timing violation is 50-60% of the clock period.

The above two scenarios need different approaches. 

Hint: How will you fix if you are supposed to make change during one of these stages/phases of design

- Micro-Architecture

- RTL Design 

- Synthesis

- Place and Route

- ECO

Interview Question 42: Design Moving Average Calculator

Moving average = Sum of (number_in_1 + ...................+ number_in_N) / N

Assume that you need to calculate the moving average over 256 last numbers.

Followup questions: 

- Design a parameterized RTL which can be used for any number

- What is the width of incoming numbers? (parameterized)

- Is there any restriction on the size of the design?

    . How restriction on size will change design and accuracy?

Interview Question 40: Design a Data Collector Machine

 You are tasked to create a Data Collector Machine in Verilog as shown below. How will you approach this design?

Assume clock and reset are provided. D7 - D0 are 8-bit buses accompanied by respective byte_enable bits to qualify them. Once you receive s "start" pulse you should start storing incoming bytes in memory. Once you receive the "end" pulse you can stop gathering data bytes and start sending them out.

Assume that Dout is a 64 Byte bus.

Scenario one: Bytes are valid contiguously. This means that if beN is valid then it is assumed that beN-1 is also valid. For example, if be3 is asserted then you can safely assume that be2, be1, and be0 are also asserted. This means that there are no "holes" in the byte formation.

Scenario two: Byte enables can be non-contiguous. There will be holes in the byte formation. In this case, you need to "gather" and "pack" the bytes before writing them to memory.

Interview Question 30: Find the smallest two numbers from the input stream

 

You need to design a module that samples an 8-bit number when valid_in is asserted. You need to find out the two smallest numbers and present them at the output. 

Followup questions during answering:

• Is "0" a default smallest number?
• No. This will end up adding output valid for the output ports.

Interview Question 29: Find the function of the module

 

This interview question is simple. You are asked to guess the functionality of this module. I think the question is very simple. It is designed to check your attitude and approach to solve a problem. It is checking your grit. Give it a try. 

module Guess (

   input   [3:0] data,

   output  [2:0] guess,

);

logic a,b,c,d;

assign {a,b,c,d} = data[3:0];

assign guess[0] = ^data;

assign guess[1] =  ((a ^ b) & (c | d)) |

                           ((a ^ c) & (b | d)) |

                           ((a ^ d) & (b | c)) |

                           ((b ^ c) & (a | d)) |

                           ((b ^ d) & (a | c)) |

                           ((c ^ d) & (a | b)) ;

assign guess[2] = &data;

endmodule

Interview Question 28: Communicate with least amount of wires

Here is another real-life scenario. Host talks to the first Chip-1 over a standard and wide interface. The host was also supposed to talk to Chip-2 over the same interface. Chip-2 was pin constrained, so it was decided to connect Chip-2 to Chip-1 and create a copy of config and status registers on Chip-1 so that host can read it.

Can you design a very simple interface between these two chips with just 2-3 wires? Power is not an issue. Timing is not an issue as the frequency is low around 100MHz. The goal is to create a quick and dirty solution.

Ignore I2C solution as you don't want to invest time in buying IP and integrating it.

Interview Question 26: Sneak CPU Read Writes

Here is an old design in which left side port is continuously performing read or write to the single port memory every clock. When there is a bubble in activity a CPU Read or Write is sneaked in.

Now the system requirements have changed and pretty much every clock read and writes are sent through the main path. CPU port is getting timed out. How do you solve this issue? 

You are not allowed to double the clock or change memory to dual port.

IEEE 1800-2012 is available freely

In this week's DCon 2013 Accellera Systems Initiative announced that IEEE 1800 SystemVerilog Language Reference Manual will be available free of charge. Here is the link.
http://standards.ieee.org/getieee/1800/download/1800-2012.pdf