Design a module that finds the faster clock between two different clocks. The output A_faster_than_B asserts "1" when fA > fB and asserts "0" when fB > fA along with valid.
Followup questions:
- How will you handle when clocks are almost the same or the same? How will you indicate the output in this case?
- How will update the design if asked to find and indicate the frequency of the clocks?
1 comment:
module dut ( input clk_A, input clk_B, output A_faster_than_B, output valid);
reg [1:0] count_A=0;
reg [1:0] count_B=0;
localparam COUNT=2'b10;
always@(posedge clk_A) if (count_A != COUNT) count_A <= count_A+1'b1;
always@(posedge clk_B) if (count_B != COUNT) count_B <= count_B+1'b1;
assign valid=(count_A == COUNT || count_A == COUNT)?1:0;
assign A_faster_than_B=(valid)?((count_A>=count_B)?1:0):0;
endmodule
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