This is a simple microarchitecture problem. You are asked to design a data splitter. It accepts 700-bit-wide data and outputs 1 or more chunks. In the worst case, it should spit out 4 data chunks.

The diagram below shows slightly more details. You need to create a struct to make sure you understand the problem correctly. The incoming data contains 32 chunks of 20-bit data (pointers??). One field in the header indicates the number of data chunks. It decides whether to output just one chunk of data or multiple chunks. The diagram shows the worst-case scenario when num_data=32. Each chunk can carry 8 pieces of data, so you will end up transmitting 4 chunks of data over 4 clocks.

Some fields in the header also indicate the destination. They will be used to decide where to send the data: Data_Out_0 or Data_Out_1.

With this information, create a microarchitecture.

Issue 1: As you are creating 4 clocks' worth of output transactions with 1 clock of input data, you will have a backpressure issue. How will you solve it? Where will you put your FIFOs?

Issue 2: When this splitter is transmitting data on one output port, the other output port is unused for 4 or more clocks. How do you modify the design so that both output ports stay busy?

Imagine a worst-case scenario in which inputs arrive in such a way that their output ports alternate. You can see that if one output port back pressures, the second port stalls or starves, even if it is not congested. How to avoid this head-of-the-line blocking?