Interview Question 40: Design a Data Collector Machine

 You are tasked to create a Data Collector Machine in Verilog as shown below. How will you approach this design?

Assume clock and reset are provided. D7 - D0 are 8-bit buses accompanied by respective byte_enable bits to qualify them. Once you receive s "start" pulse you should start storing incoming bytes in memory. Once you receive the "end" pulse you can stop gathering data bytes and start sending them out.

Assume that Dout is a 64 Byte bus.

Scenario one: Bytes are valid contiguously. This means that if beN is valid then it is assumed that beN-1 is also valid. For example, if be3 is asserted then you can safely assume that be2, be1, and be0 are also asserted. This means that there are no "holes" in the byte formation.

Scenario two: Byte enables can be non-contiguous. There will be holes in the byte formation. In this case, you need to "gather" and "pack" the bytes before writing them to memory.

Interview Question 39: Compute Sum of Differences.

 You need to compute the Sum of Differences for the given two matrices.

Output = ABS(A00-B00) + .... + ABS(A03-B03) + ........+ ABS(A30-B30) + .... + ABS(A33-B33)

Each entry is an 8-bit unsigned integer. 

Questions you should be asking:

- Are all the values are available immediately or they arrive at different times?

- How many clocks are allowed to compute? (1/2/4/16)

    . The answer will change your micro-architecture of design

Hints:

- Design a simple SOD design for just two 8-bit inputs. This can become a building block.

- Give attention to the widths of outputs of each block.

- What will change if the design can not fit in the required number of clocks? (pipelining)

Interview Question 38: What are the issues with this logic?

This is one of the common questions asked to check your experience or awareness of CDC. (Clock Domain Crossing) Can you find at least two issues?

Interview Question 37: Swap contents of two register without having a third intermediate register

 This is a favorite question of software folks. They will ask you to swap two registers using a sequential machine. 

RTL designers get irritated as we can do it simply in one clock by doing the following.

always @(posedge clock) begin
    A <= B;
    B <= A;
end

Ask follow-up questions. You will hear something like this. 

"How many clocks this operation takes is not a concern. You may take 2-3 clocks to complete this operation."

This is a hint along with the ALU block.

Interview Question 36: Design a pulse width based filter

 This question is a twist on the last question. You need to create a positive edge detector but only when the input is wider than 2 clock widths.

A waveform is shown below to specify the behavior accurately.

Interview Question 35: Design a posedge detector

 Design a positive edge detector module as shown below.

A timing diagram is shown below to illustrate the behavior. You can use that to create a testbench and verify your Verilog RTL code.

Interview Question 34: Synchronize reset to a slower clock domain

 You are tasked to design a reset synchronizer. The reset is provided in the core clock domain which is a 100MHz clock domain. You need to create a reset for IP in another part of the design that is working at 1MHz.  

A timing diagram is provided to give you an idea. It is scaled back to a ratio of 6 to fit it in the diagram.