Interview Question 35: Design a posedge detector

 Design a positive edge detector module as shown below.

A timing diagram is shown below to illustrate the behavior. You can use that to create a testbench and verify your Verilog RTL code.

Interview Question 13: Random Number Generation

Random numbers are needed in verification to exercise various corner cases in a test benches. Every test bench is unique. Every test scenario calls for the different kinds of random number generation. Here are two common scenarios encountered in verification. The later question helps is constrained random verification.

- Create a function (or task / module) to generate 256 “unique” random numbers.
  The generated number is unsigned 8 bit number. A simple $random call may generate repeated numbers. Your task is to create a function which guarantees unique numbers in first set of 256 numbers. The next batch may repeat the whole set.

- Design a module which generates weighted random (pseudo random) numbers. Instead of generating unique numbers this time your task is to generate a small set of numbers randomly distributed but with agreed weight-age  Out of all 100 numbers generated the distribution of numbers should be as follows.

Numbers	Distribution
0	5%
7	20%
35	25%
145	30%
244	20%
Total	100%

Interview Question 3: Random number generator with weights

Generate random numbers such that they follow certain needed pattern. For example out of 100 generated random numbers.

35% should be    5
20% should be   25
10% should be   123
35% should be   73

The naming is confusing. The set of output numbers is small. You are just creating numbers from a small set {5,25,123,73} but the sequence of output numbers is random or unpredictable.

Can you think of any application or test bench mechanism where such numbers are needed?