Interview Question 26: Sneak CPU Read Writes

Here is an old design in which left side port is continuously performing read or write to the single port memory every clock. When there is a bubble in activity a CPU Read or Write is sneaked in.

Now the system requirements have changed and pretty much every clock read and writes are sent through the main path. CPU port is getting timed out. How do you solve this issue? 

You are not allowed to double the clock or change memory to dual port.

Interview Question 25: Odd number finder

Design a hardware module which reads a long magnetic Tape. The tape has 2n + 1 numbers. The numbers are grouped as n pairs. The number reader reads the magnetic tape and converts them to 16-bit binary numbers.

How will you design this Number Reader Hardware to find out the additional odd number which is not part of the number pairs? You can use 32x16 bit registers and plenty of logic gates.

Interview Question 24: Sequence Detector

Create a block which detects two or more 1s in the last 3 clocks.

Find a brute force / clever solution as well as one with state machine design approach.

Interview Question 23: Micro Architect a Counters Block

Micro-architect a counters module as shown in above picture.

This module contains a large number of counters using an SRAM. This memory takes two clocks to write and three clocks to read data. You need to read counter value based on provided Address_In, perform increment or decrement operation, and then write it back to the same location to update the value. The output ports provide updated counter values.

This may seem like a simple read-modify-write operation but account for corner cases like consecutive operations performed on the same address.

Interview Question 22: Micro Architect a Block

You are asked to micro-architect this block. The goal is to keep performance high enough to keep Encryption Engine busy all the time.

Assumptions:

- External memory (DDR) has 16Gbps bandwidth but 45 clocks latency

- DMA description memory has 6 clocks of latency and needs 6 clocks to fetch the whole descriptor.

- Encryption engine provides data in next clock.

This question shows the experience and maturity of the designer. The key concepts which one should look for are

- Latency

- Performance

- Pipelining of memory operations

- FIFO sizing

- State Machines etc

Interview Question 21: Find more than two 1s in the input vector

- Try to solve the problem using 2-3 different ways with different complexities. 

Interview Question 20 : Design Asynchronous FIFO using memory

Design a 16K deep and 8 bit wide Async fifo. As FIFO is deep you need to use memory.
- What are various ways to implement this?

• faster memory
• 2 or more copies or pieces of memories

- How you can implement this just by using a single port memory? Assume that memory can not be run on higher frequency.
Hint: Wider memory.