Interview Question 20 : Design Asynchronous FIFO using memory

Design a 16K deep and 8 bit wide Async fifo. As FIFO is deep you need to use memory.
- What are various ways to implement this?

• faster memory
• 2 or more copies or pieces of memories

- How you can implement this just by using a single port memory? Assume that memory can not be run on higher frequency.
Hint: Wider memory.

Interview Question 19: Gate level logic design

Observe following timing diagram and create logic in gate level as well as in Verilog

Interview Question 18: Performance counters

A typical memory network is shown above. Device 1 can read/write the data in following 3 ways.

• from off chip memory
• from on chip cache
• from on chip other slower devices

Design a logic which will provide Average Latency for these accesses.

What are the various factors which will be needed consideration?

Hints:
- Can you use just one counter or set of counters to observe one transaction at a time?
- How can you use many counters to observe multiple transactions simultaneously?
- Can you use no individual counters and still get very good results?

Interview Question 17: Create a Link List in hardware

Q : Create a link list in hardware which supports following operations

- create_list

- append_item (data_in)

- pop_item (data_out)

- add_item (physical_address)

- remove_item (physical_address)

You will have following port list

Inputs:

- clock, reset

- command // as explained above

- data_in // 32Bytes or larger data which will be written in separate memory 

               // other than link list structure

- data_out // this will be result of pop_item command.

IEEE 1800-2012 is available freely

In this week's DCon 2013 Accellera Systems Initiative announced that IEEE 1800 SystemVerilog Language Reference Manual will be available free of charge. Here is the link.
http://standards.ieee.org/getieee/1800/download/1800-2012.pdf

The articles I read - 3: Moore's Law: The rule that really matters in tech

In 1965, Intel co-founder Gordon Moore foresaw an inexorable rise in chip power that eventually delivered the computer to your pocket. While long in the tooth, Moore's prediction still has plenty of life in it. Here's why.
http://news.cnet.com/8301-11386_3-57526581-76/moores-law-the-rule-that-really-matters-in-tech/

The articles I read - 2: Nulticore

As the number of cores grow from two to 64 performance plummets by a factor of five. Additional processors nullify each other. The author called it the Nulticore Effect. Read the full article here.
http://www.embedded.com/design/mcus-processors-and-socs/4008183/The-Nulticore-effect 

This article sites IEEE Spectrum’s article.
http://spectrum.ieee.org/computing/hardware/multicore-is-bad-news-for-supercomputers

In past there had many few attempts to solve such issues. Berkeley IRAM was one of the significant one.
Few advances in chip fabrication technology as well as design practices in recent past can fuel new good ideas. Here is one of my idea.

The diagram above shows the concept where multiple processors access a Unified memory Complex which provides boost in memory throughput. The memory shown in the middle can be a monolithic single chip or collection of separate unit depending upon technology limitations. 

Each Processor directly talks to dedicated Cache. It also accesses a copy of common memory devoted to it. These copies are kept in sync using an crossbar interconnect, possibly using an asynchronous design techniques.

All processors should be able to read the memory individually giving Nx speedup. The writes are also can be done individually at Nx speed as long as they are done to different area of address map. The asynchronous sync machine will sync up all N copies of memories in background using faster backdoor channels.