Interview Question 38: What are the issues with this logic?

This is one of the common questions asked to check your experience or awareness of CDC. (Clock Domain Crossing) Can you find at least two issues?

Interview Question 37: Swap contents of two register without having a third intermediate register

 This is a favorite question of software folks. They will ask you to swap two registers using a sequential machine. 

RTL designers get irritated as we can do it simply in one clock by doing the following.

always @(posedge clock) begin
    A <= B;
    B <= A;
end

Ask follow-up questions. You will hear something like this. 

"How many clocks this operation takes is not a concern. You may take 2-3 clocks to complete this operation."

This is a hint along with the ALU block.

Interview Question 36: Design a pulse width based filter

 This question is a twist on the last question. You need to create a positive edge detector but only when the input is wider than 2 clock widths.

A waveform is shown below to specify the behavior accurately.

Interview Question 35: Design a posedge detector

 Design a positive edge detector module as shown below.

A timing diagram is shown below to illustrate the behavior. You can use that to create a testbench and verify your Verilog RTL code.

Interview Question 34: Synchronize reset to a slower clock domain

 You are tasked to design a reset synchronizer. The reset is provided in the core clock domain which is a 100MHz clock domain. You need to create a reset for IP in another part of the design that is working at 1MHz.  

A timing diagram is provided to give you an idea. It is scaled back to a ratio of 6 to fit it in the diagram.

Interview Question 33: What's wrong with this design?

 Look and analyze the following design. What can wrong?

Followup question: How do you fix this?

Interview Question 32: Inverse the linked list

Consider the following pre-existing linked list(s) in a 32K deep memory. 

Design a module that takes in a head pointer (starting address) of a linked list and inverses it. Once done, it asserts a done signal with the new head pointer, which was earlier the tail pointer.

- Write pseudo code

- Draw a state diagram if you want to implement using FSM or timing diagram

- Write Verilog code.

For example, in a provided example when the head_pointer is provided as A, you should provide D as the New_Head_Pointer and assert done signal.