Interview Question 32: Inverse the linked list

Consider the following pre-existing linked list(s) in a 32K deep memory. 

Design a module that takes in a head pointer (starting address) of a linked list and inverses it. Once done, it asserts a done signal with the new head pointer, which was earlier the tail pointer.

- Write pseudo code

- Draw a state diagram if you want to implement using FSM or timing diagram

- Write Verilog code.

For example, in a provided example when the head_pointer is provided as A, you should provide D as the New_Head_Pointer and assert done signal.

Interview Question 31: Create a Verilog module to drive a PWM signal to the motor.

  

Create a module to drive a motor with a PWM output. You are provided an N-bit bus to indicate duty cycle. This fairly open-ended question. You can add more ports to time the circuit etc.

Follow-up questions: How will you treat the feedback signal from the motor?

Hint: You are expected to ask about frequency ratios and perform synchronization etc.

Interview Question 30: Find the smallest two numbers from the input stream

 

You need to design a module that samples an 8-bit number when valid_in is asserted. You need to find out the two smallest numbers and present them at the output. 

Followup questions during answering:

• Is "0" a default smallest number?
• No. This will end up adding output valid for the output ports.

Interview Question 29: Find the function of the module

 

This interview question is simple. You are asked to guess the functionality of this module. I think the question is very simple. It is designed to check your attitude and approach to solve a problem. It is checking your grit. Give it a try. 

module Guess (

   input   [3:0] data,

   output  [2:0] guess,

);

logic a,b,c,d;

assign {a,b,c,d} = data[3:0];

assign guess[0] = ^data;

assign guess[1] =  ((a ^ b) & (c | d)) |

                           ((a ^ c) & (b | d)) |

                           ((a ^ d) & (b | c)) |

                           ((b ^ c) & (a | d)) |

                           ((b ^ d) & (a | c)) |

                           ((c ^ d) & (a | b)) ;

assign guess[2] = &data;

endmodule

Interview Question 28: Communicate with least amount of wires

Here is another real-life scenario. Host talks to the first Chip-1 over a standard and wide interface. The host was also supposed to talk to Chip-2 over the same interface. Chip-2 was pin constrained, so it was decided to connect Chip-2 to Chip-1 and create a copy of config and status registers on Chip-1 so that host can read it.

Can you design a very simple interface between these two chips with just 2-3 wires? Power is not an issue. Timing is not an issue as the frequency is low around 100MHz. The goal is to create a quick and dirty solution.

Ignore I2C solution as you don't want to invest time in buying IP and integrating it.

Interview Question 27: Detect ASIC Orientation before it burns

This is a real-life problem. An incompletely marked ASICs are put on tester socket. They get burnt if incorrectly oriented. These chips are very expensive.

How will you design these ASICs and surrounding tester board logic so that these ASICs are not powered up if they are incorrectly positioned?

Assume that budget is relaxed and you are free to add extra pins as well extra chip (FPGAs, CPLDs) on board to make this possible.

Interview Question 26: Sneak CPU Read Writes

Here is an old design in which left side port is continuously performing read or write to the single port memory every clock. When there is a bubble in activity a CPU Read or Write is sneaked in.

Now the system requirements have changed and pretty much every clock read and writes are sent through the main path. CPU port is getting timed out. How do you solve this issue? 

You are not allowed to double the clock or change memory to dual port.