Interview Question 8: Sneaking CPU read/writes when continuous Memory Read Writes are going on

With the advent of increased performance needs new design challenges arise. This questions deals with one of such problem. A single port memory is continuously accessed by surrounding data plane blocks. They are accessing memory in continuous fashion. For example W-R-W-R.... There is no empty clock cycle to waste. 

The software wants to access this memory through CPU read/writes intermittently. Usually a simple mechanism using a state machine can be used to sneak in CPU access when no data plane access is going on. The problem arises when when this request gets timed out as every clock is being used by data planes accesses. How does one resolve this problem?

Changing single port memory to dual port memory seems to be easy solution but what if it is prohibitively expensive and not allowed. As design geometries are also stretched to the limit, increasing/doubling clock rate of memory is also ruled out.

How will you approach this practical problem?

Interview Question 7: Enhance the memory

You are given a one port memory block as shown below.

In past you used this memory to design an application where you performed one read or write operation every clock. Now in next generation product you are asked to double the performance. How will you accomplish it? Brainstorm multiple scenarios.
For example:

1. How will you modify the design if you could double the clock at which memory can run?

2. What if you can not double the clock speed? How will you modify the design if you are asked to use memory at the same clock period as the surrounding logic.

I know, it is difficult to take out juice from the memory like this. What if you are asked just to allow (WRx + RDy) or (RD0 + RD1) combinations only? You may also use more than one memory to solve this problem.

Interview Question 6: 7 bit 1’s counter using 1 bit adders.

You are given a basic 1 bit adder block as shown below. 

How can you use this building block to create a module which finds out number of 1s in a 7 bit input?

Interview Question 5: Design / Architect a solution

Design a solution (state machine, timing diagrams etc) for following problem.

Followup question: What are the possible error conditions. How to  find and recover from them?

Interview Question 4: Digital Delay

You are asked to design a 512 Clock Digital delay. A 32 bit data is fed to this module. It comes out after 512 clocks at the output.
- What is the most efficient way to design this block?
- What happens if data widths of input and output change? For example {32,64} or {64,32}?

- Where such huge delays are used?

Interview Question 3: Random number generator with weights

Generate random numbers such that they follow certain needed pattern. For example out of 100 generated random numbers.

35% should be    5
20% should be   25
10% should be   123
35% should be   73

The naming is confusing. The set of output numbers is small. You are just creating numbers from a small set {5,25,123,73} but the sequence of output numbers is random or unpredictable.

Can you think of any application or test bench mechanism where such numbers are needed?

Interview Question 2: Find the largest bit in 64 bit number

Problem: You are asked to design a hardware which takes in a 64 bit number and finds out the largest position of  “1”.  For example if the input number is “00001010101111000” then the output should assert “1100” or 12 in decimal.

You can also dive deeper and find out corner cases and suggest how to fix them.
Also try to create solution which will be synthesis friendly and produces smallest and fastest solution.