Monday, June 24, 2013

Interview Question 18: Performance counters





A typical memory network is shown above. Device 1 can read/write the data in following 3 ways.
  • from off chip memory
  • from on chip cache
  • from on chip other slower devices
Design a logic which will provide Average Latency for these accesses.
What are the various factors which will be needed consideration?

Hints:
- Can you use just one counter or set of counters to observe one transaction at a time?
- How can you use many counters to observe multiple transactions simultaneously?
- Can you use no individual counters and still get very good results?



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