Interview Question 20 : Design Asynchronous FIFO using memory

Design a 16K deep and 8 bit wide Async fifo. As FIFO is deep you need to use memory.
- What are various ways to implement this?

• faster memory
• 2 or more copies or pieces of memories

- How you can implement this just by using a single port memory? Assume that memory can not be run on higher frequency.
Hint: Wider memory.

Interview Question 19: Gate level logic design

Observe following timing diagram and create logic in gate level as well as in Verilog

Interview Question 18: Performance counters

A typical memory network is shown above. Device 1 can read/write the data in following 3 ways.

• from off chip memory
• from on chip cache
• from on chip other slower devices

Design a logic which will provide Average Latency for these accesses.

What are the various factors which will be needed consideration?

Hints:
- Can you use just one counter or set of counters to observe one transaction at a time?
- How can you use many counters to observe multiple transactions simultaneously?
- Can you use no individual counters and still get very good results?

Interview Question 17: Create a Link List in hardware

Q : Create a link list in hardware which supports following operations

- create_list

- append_item (data_in)

- pop_item (data_out)

- add_item (physical_address)

- remove_item (physical_address)

You will have following port list

Inputs:

- clock, reset

- command // as explained above

- data_in // 32Bytes or larger data which will be written in separate memory 

               // other than link list structure

- data_out // this will be result of pop_item command.

IEEE 1800-2012 is available freely

In this week's DCon 2013 Accellera Systems Initiative announced that IEEE 1800 SystemVerilog Language Reference Manual will be available free of charge. Here is the link.
http://standards.ieee.org/getieee/1800/download/1800-2012.pdf