Interview Question 24: Sequence Detector

Create a block which detects two or more 1s in the last 3 clocks.

Find a brute force / clever solution as well as one with state machine design approach.

Interview Question 23: Micro Architect a Counters Block

Micro-architect a counters module as shown in above picture.

This module contains a large number of counters using an SRAM. This memory takes two clocks to write and three clocks to read data. You need to read counter value based on provided Address_In, perform increment or decrement operation, and then write it back to the same location to update the value. The output ports provide updated counter values.

This may seem like a simple read-modify-write operation but account for corner cases like consecutive operations performed on the same address.

Interview Question 22: Micro Architect a Block

You are asked to micro-architect this block. The goal is to keep performance high enough to keep Encryption Engine busy all the time.

Assumptions:

- External memory (DDR) has 16Gbps bandwidth but 45 clocks latency

- DMA description memory has 6 clocks of latency and needs 6 clocks to fetch the whole descriptor.

- Encryption engine provides data in next clock.

This question shows the experience and maturity of the designer. The key concepts which one should look for are

- Latency

- Performance

- Pipelining of memory operations

- FIFO sizing

- State Machines etc

Interview Question 21: Find more than two 1s in the input vector

- Try to solve the problem using 2-3 different ways with different complexities. 

Interview Question 20 : Design Asynchronous FIFO using memory

Design a 16K deep and 8 bit wide Async fifo. As FIFO is deep you need to use memory.
- What are various ways to implement this?

• faster memory
• 2 or more copies or pieces of memories

- How you can implement this just by using a single port memory? Assume that memory can not be run on higher frequency.
Hint: Wider memory.

Interview Question 19: Gate level logic design

Observe following timing diagram and create logic in gate level as well as in Verilog

Interview Question 18: Performance counters

A typical memory network is shown above. Device 1 can read/write the data in following 3 ways.

• from off chip memory
• from on chip cache
• from on chip other slower devices

Design a logic which will provide Average Latency for these accesses.

What are the various factors which will be needed consideration?

Hints:
- Can you use just one counter or set of counters to observe one transaction at a time?
- How can you use many counters to observe multiple transactions simultaneously?
- Can you use no individual counters and still get very good results?