VLSI Interview Questions by Rajesh Bawankule

 Design a positive edge detector module as shown below. A timing diagram is shown below to illustrate the behavior. You can use that to crea...

 You are tasked to design a reset synchronizer. The reset is provided in the core clock domain which is a 100MHz clock domain. You need to c...

 Look and analyze the following design. What can wrong? Followup question: How do you fix this?

Consider the following pre-existing linked list(s) in a 32K deep memory.  Design a module that takes in a head pointer (starting address) of...

   Create a module to drive a motor with a PWM output. You are provided an N-bit bus to indicate duty cycle. This fairly open-ended question...

  You need to design a module that samples an 8-bit number when valid_in is asserted. You need to find out the two smallest numbers and pres...

  This interview question is simple. You are asked to guess the functionality of this module. I think the question is very simple. It is des...