VLSI Interview Questions by Rajesh Bawankule
Wednesday, February 1, 2023
ChatGPT and Verilog RTL
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A month ago, I heard about ChatGPT. I wanted to know how it will create Verilog RTL code. When I got to log in from their waitlist, I tried ...
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Wednesday, October 14, 2020
Interview Question 47: Multi Clock Sync Pulse
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Design a module as shown below. The input sync_A gets asserted for some (say 3) clocks in the clk_A domain. The output sync_B should also a...
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Tuesday, September 15, 2020
Interview Question 46: What is wrong with this design?
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Study the provided block diagram of a chip-level design. Each square has one clock delay associated with it. What can go wrong with this ty...
Monday, August 3, 2020
Interview Question 45: Find faster clock
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Design a module that finds the faster clock between two different clocks. The output A_faster_than_B asserts "1" when fA > fB ...
Monday, July 6, 2020
Interview Question 44: Fix the Timing Issue
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Consider a design where two modules on the chip communicate with each other over a bus using a protocol like AXI. Data from block 1 is consu...
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Saturday, June 6, 2020
Interview Question 43: Improve the data pipeline
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This is a data pipeline question. The existing design has a simple data pipeline as shown below. Data_in is a wide bus that comes along wit...
Wednesday, May 20, 2020
Interview Question 42: Design Moving Average Calculator
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Moving average = Sum of (number_in_1 + ...................+ number_in_N) / N Assume that you need to calculate the moving average over 256 l...
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