VLSI Interview Questions by Rajesh Bawankule

 This is a simple microarchitecture problem. You are asked to design a data splitter. It accepts 700-bit-wide data and outputs 1 or more chu...

A month ago, I heard about ChatGPT. I wanted to know how it will create Verilog RTL code. When I got to log in from their waitlist, I tried ...

 Design a module as shown below. The input sync_A gets asserted for some (say 3) clocks in the clk_A domain. The output sync_B should also a...

 Study the provided block diagram of a chip-level design. Each square has one clock delay associated with it. What can go wrong with this ty...

 Design a module that finds the faster clock between two different clocks. The output A_faster_than_B asserts "1" when fA > fB ...

Consider a design where two modules on the chip communicate with each other over a bus using a protocol like AXI. Data from block 1 is consu...

 This is a data pipeline question. The existing design has a simple data pipeline as shown below. Data_in is a wide bus that comes along wit...