Divide by 1.5 Counter
This is one of the favourite questions asked in interviews. One of the best answers I found was in Xilinx’s Xcell magazine by one of my favorite authors, Peter Alfke. Check out his article called “Unusual Dividers” on page 30.
http://www.xilinx.com/publications/archives/xcell/Xcell33.pdf
This blog post is devoted to him. He died yesterday. Peter’s greatest talent was not simply that he was an FPGA expert but that he could communicate very technical content in a very practical and concise way.
“He was very proud that he came from a long line of educators,” said Carter. “His ability to take complex ideas and communicate them very clearly was really quite remarkable, especially when you realize that English was his second language. He liked to share his wisdom and never did it in arrogant manner. He was a fabulous diplomat, very approachable, very welcoming…a true gentleman.”
At lunchtime at Xilinx, Peter always drew a crowd of admiring friends to his table and there was always room for more. It was not uncommon to find 10 or more people sitting at a table built for 4 listening to Peter’s advice and sharing stories about all things under the sun.
Alfke is survived by his wife, son and daughter and two grandchildren. He was 79.
Read EETimes article , blog entry and EETimes news article for more details.
The first known FIFO implemented in electronics was done by Peter Alfke in 1969 at Fairchild Semiconductors. More details
Here is link to his patent on FIFO.
First-in, first-out buffer system in an integrated circuit
The articles I read - 2: Moving data across asynchronous clock boundaries
What strategy best addresses a situation where parallel data must pass across a clock domain boundary? The traditional method is to generate a flag and to use a handshake sequence.
When the transmitter has parallel data ready for transfer,it creates a rising edge on the READY line, which in turn sets flag F telling the receiver that data is available. The receiver scans F continuously and, after finding it high, accepts the stable parallel data and then creates a rising edge of ACK, which sets flip-flop A. This resets F, which in turn resets A. This particular design makes no assumptions about any phase or frequency relationship between the transmit and receive clocks. Such generality dictates a design using a benign
controlled race condition between the two flip-flops. A reasonable loop delay can conveniently be inserted between F and the reset of A. In a less generic design, this delay might be implemented as one period of either the transmit or receive clock.
This traditional handshake requires both sides to poll the flag F. The transmitter must change parallel data only when F is low, and the receiver must accept data only when F is high. This requirement results in a safe but slow data transfer. However, speedier ways to transfer data across an asynchronous clock boundary exist.
Peter Alfke's article was originally published in Integrated System Design magazine in 2000. A pdf of this article is available here. An html version of original article is archived here.
