Interview Question 43: Improve the data pipeline

 This is a data pipeline question. The existing design has a simple data pipeline as shown below.

Data_in is a wide bus that comes along with a qualifier valid_in every clock. The pipeline stage which is shown as a box is straightforward and just passes data and a valid bit to the next stage. In the above picture, the blue boxes are ones that have data and valid=1. The read ones are just passing valid=0 with old data.

When the pause is asserted by the block on the right side which is receiving this data, the whole pipeline freezes. You can see that only two out of six stages contain real data. The Pause is passed as it is to the left side which stops providing data.

Your job is to fix these pipeline stages or even re-write them so that when the pause is asserted the design continues to absorb data from the left side till all pipe stages are full and then assert the back_pressure signal. In the above example, this will happen after 3 clocks.