Interview Question 47: Multi Clock Sync Pulse

 Design a module as shown below. The input sync_A gets asserted for some (say 3) clocks in the clk_A domain. The output sync_B should also assert for exactly the same number of clocks but in the clk_B domain.

The timing diagram is shown below.

Followup questions:

- Is fA/fB ratio fixed or it is unknown?

  .The answer to this question will decide which CDC approach you should take.

- Is the number of clocks fixed or variable or it can vary on the fly or is it configurable?

  . The answer to this question will decide which approach you take?

Interview Question 46: What is wrong with this design?

 Study the provided block diagram of a chip-level design. Each square has one clock delay associated with it. What can go wrong with this type of design? How will you fix it? How it will affect the overall design?

Interview Question 45: Find faster clock

 Design a module that finds the faster clock between two different clocks. The output A_faster_than_B asserts "1" when fA > fB and asserts "0" when fB > fA along with valid. 

Followup questions:

- How will you handle when clocks are almost the same or the same? How will you indicate the output in this case?

- How will update the design if asked to find and indicate the frequency of the clocks?

Interview Question 44: Fix the Timing Issue

Consider a design where two modules on the chip communicate with each other over a bus using a protocol like AXI. Data from block 1 is consumed by block 2 when both valid and ready are asserted.

The timing shown below shows how this protocol works.

After Synthesis and Place & Route, you find out that a valid/ready handshake is not meeting timing. How will you fix it?

These two blocks are IPs from a vendor. Though you have access to RTL, you can not change them radically. You are allowed to add some glue logic in between. This is a fairly open-ended question. Your past experience will result in multiple ideas.

How will you attach this problem in these two scenarios?

a) Timing violation is just 5-10% of the clock period.

b) Timing violation is 50-60% of the clock period.

The above two scenarios need different approaches. 

Hint: How will you fix if you are supposed to make change during one of these stages/phases of design

- Micro-Architecture

- RTL Design 

- Synthesis

- Place and Route

- ECO

Interview Question 43: Improve the data pipeline

 This is a data pipeline question. The existing design has a simple data pipeline as shown below.

Data_in is a wide bus that comes along with a qualifier valid_in every clock. The pipeline stage which is shown as a box is straightforward and just passes data and a valid bit to the next stage. In the above picture, the blue boxes are ones that have data and valid=1. The read ones are just passing valid=0 with old data.

When the pause is asserted by the block on the right side which is receiving this data, the whole pipeline freezes. You can see that only two out of six stages contain real data. The Pause is passed as it is to the left side which stops providing data.

Your job is to fix these pipeline stages or even re-write them so that when the pause is asserted the design continues to absorb data from the left side till all pipe stages are full and then assert the back_pressure signal. In the above example, this will happen after 3 clocks.

Interview Question 42: Design Moving Average Calculator

Moving average = Sum of (number_in_1 + ...................+ number_in_N) / N

Assume that you need to calculate the moving average over 256 last numbers.

Followup questions: 

- Design a parameterized RTL which can be used for any number

- What is the width of incoming numbers? (parameterized)

- Is there any restriction on the size of the design?

    . How restriction on size will change design and accuracy?

Interview Question 41: Design a circuit to calculate square of a number

Create micro-architecture and write an RTL code for a design that calculates the square of a given number.

Caveat: It should not use any multiplier operation. It does not have to be done in one clock cycle.

Interview Question 40: Design a Data Collector Machine

 You are tasked to create a Data Collector Machine in Verilog as shown below. How will you approach this design?

Assume clock and reset are provided. D7 - D0 are 8-bit buses accompanied by respective byte_enable bits to qualify them. Once you receive s "start" pulse you should start storing incoming bytes in memory. Once you receive the "end" pulse you can stop gathering data bytes and start sending them out.

Assume that Dout is a 64 Byte bus.

Scenario one: Bytes are valid contiguously. This means that if beN is valid then it is assumed that beN-1 is also valid. For example, if be3 is asserted then you can safely assume that be2, be1, and be0 are also asserted. This means that there are no "holes" in the byte formation.

Scenario two: Byte enables can be non-contiguous. There will be holes in the byte formation. In this case, you need to "gather" and "pack" the bytes before writing them to memory.

Interview Question 39: Compute Sum of Differences.

 You need to compute the Sum of Differences for the given two matrices.

Output = ABS(A00-B00) + .... + ABS(A03-B03) + ........+ ABS(A30-B30) + .... + ABS(A33-B33)

Each entry is an 8-bit unsigned integer. 

Questions you should be asking:

- Are all the values are available immediately or they arrive at different times?

- How many clocks are allowed to compute? (1/2/4/16)

    . The answer will change your micro-architecture of design

Hints:

- Design a simple SOD design for just two 8-bit inputs. This can become a building block.

- Give attention to the widths of outputs of each block.

- What will change if the design can not fit in the required number of clocks? (pipelining)

Interview Question 38: What are the issues with this logic?

This is one of the common questions asked to check your experience or awareness of CDC. (Clock Domain Crossing) Can you find at least two issues?