Design a module as shown below. The input sync_A gets asserted for some (say 3) clocks in the clk_A domain. The output sync_B should also assert for exactly the same number of clocks but in the clk_B domain.
The timing diagram is shown below.
- Is fA/fB ratio fixed or it is unknown?
.The answer to this question will decide which CDC approach you should take.
- Is the number of clocks fixed or variable or it can vary on the fly or is it configurable?
. The answer to this question will decide which approach you take?
