Consider a design where two modules on the chip communicate with each other over a bus using a protocol like AXI. Data from block 1 is consumed by block 2 when both valid and ready are asserted.
The timing shown below shows how this protocol works.
After Synthesis and Place & Route, you find out that a valid/ready handshake is not meeting timing. How will you fix it?
These two blocks are IPs from a vendor. Though you have access to RTL, you can not change them radically. You are allowed to add some glue logic in between. This is a fairly open-ended question. Your past experience will result in multiple ideas.
How will you attach this problem in these two scenarios?
a) Timing violation is just 5-10% of the clock period.
b) Timing violation is 50-60% of the clock period.
The above two scenarios need different approaches.
Hint: How will you fix if you are supposed to make change during one of these stages/phases of design
- Micro-Architecture
- RTL Design
- Synthesis
- Place and Route
- ECO
