You are tasked to create a Data Collector Machine in Verilog as shown below. How will you approach this design?
Assume clock and reset are provided. D7 - D0 are 8-bit buses accompanied by respective byte_enable bits to qualify them. Once you receive s "start" pulse you should start storing incoming bytes in memory. Once you receive the "end" pulse you can stop gathering data bytes and start sending them out.
Assume that Dout is a 64 Byte bus.
Scenario one: Bytes are valid contiguously. This means that if beN is valid then it is assumed that beN-1 is also valid. For example, if be3 is asserted then you can safely assume that be2, be1, and be0 are also asserted. This means that there are no "holes" in the byte formation.
Scenario two: Byte enables can be non-contiguous. There will be holes in the byte formation. In this case, you need to "gather" and "pack" the bytes before writing them to memory.
