Consider the following pre-existing linked list(s) in a 32K deep memory.
Design a module that takes in a head pointer (starting address) of a linked list and inverses it. Once done, it asserts a done signal with the new head pointer, which was earlier the tail pointer.
- Write pseudo code
- Draw a state diagram if you want to implement using FSM or timing diagram
- Write Verilog code.
For example, in a provided example when the head_pointer is provided as A, you should provide D as the New_Head_Pointer and assert done signal.
