This is a real-life problem. An incompletely marked ASICs are put on tester socket. They get burnt if incorrectly oriented. These chips are very expensive.
How will you design these ASICs and surrounding tester board logic so that these ASICs are not powered up if they are incorrectly positioned?
Assume that budget is relaxed and you are free to add extra pins as well extra chip (FPGAs, CPLDs) on board to make this possible.
