Interview Question 26: Sneak CPU Read Writes

Here is an old design in which left side port is continuously performing read or write to the single port memory every clock. When there is a bubble in activity a CPU Read or Write is sneaked in.

Now the system requirements have changed and pretty much every clock read and writes are sent through the main path. CPU port is getting timed out. How do you solve this issue? 

You are not allowed to double the clock or change memory to dual port.

Interview Question 25: Odd number finder

Design a hardware module which reads a long magnetic Tape. The tape has 2n + 1 numbers. The numbers are grouped as n pairs. The number reader reads the magnetic tape and converts them to 16-bit binary numbers.

How will you design this Number Reader Hardware to find out the additional odd number which is not part of the number pairs? You can use 32x16 bit registers and plenty of logic gates.