You are asked to micro-architect this block. The goal is to keep performance high enough to keep Encryption Engine busy all the time.
Assumptions:
- External memory (DDR) has 16Gbps bandwidth but 45 clocks latency
- DMA description memory has 6 clocks of latency and needs 6 clocks to fetch the whole descriptor.
- Encryption engine provides data in next clock.
This question shows the experience and maturity of the designer. The key concepts which one should look for are
- Latency
- Performance
- Pipelining of memory operations
- FIFO sizing
- State Machines etc
